I haven’t used Zynq before, so maybe this suggestion is not appropriate. When we get back to the issue I will post whatever resolution we come up with. I will dig into the kernel code to see if there is a workaround. Finally, I saw this thread for Petalinux, which I was not able to locate the patch for, but it seems related. It will be fixed in the I assume you use the same interface voltage for both PHY chips.
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I will dig into the kernel code to see if there is a workaround. Note that I am using two different sub-nets – the I don’t have the Marvell datasheet handy, but recall seeing that when oinux a 1. Linux Kernel Thanks Panou.
Anyone else had it work?
net: phy: marvell: fix Marvell 88E used in SGMII mode – Patchwork
Reluctant to pursue it as we are not using Petalinux:. Finally, I saw this thread for Petalinux, which I was not able to locate the patch for, but it seems related. However, eth1 still doesn’t work correctly. Hope this helps everyone with this problem I have gotten a patch that looks like it applies to the Again, this appears to be a software issue. What other kernel settings did you have to enable to allow the Marvell 88e PHY to have the correct drivers from petalinux?
Haven’t worked on this in a couple of years.
net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]
There was a little communication confusion with Xilinx. Build the device tree blob, and copy madvell and the. Check the reset pin to the PHYs.
If they both operate at 2. It’s likely that a hardware workaround in the fabric is easier to implement than digging into the Linux core software.
This has been tested on Zynq Ultrascale with a Daughter card. Another question if I may, what about the dsa part in the tree, isn’t it required?
Linux on P4080 + external PHY through RGMII: slow ping + total freeze without error message
The device tree in the newer kernels uses the MACB drivers. I have tried the current xilinx-linux git repo, and the patch is not in that repo, nor is the patch applicable to that repo. Verified fix for this problem. This particular PHY can only be configured for address zero or one, depending on how a couple of pins are strapped. We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot.
I’ll update you when I have more information. FYI, the patch is here, but not applicable to any of the current Xilinx kernel releases: I’ve tried your device tree example as well as different examples found: Oddly, eth1 seems to receive packets even though the link is never detected.
This seems to make sense, as all the other dual phy configurations I see have PHY addresses that aren’t zero.
Linux source code: drivers/net/phy/marvell.c (v) – Bootlin
Not sure about the dsa or link. Note that it attaches a Generic PHY driver to eth1, and the phy id is: We have a custom board with a Zynq using two Marvell 88e PHYs for dual ethernet and have not been able to get eth1 up and running on xilinx-linux eth0 works fine. 881e512
Do you marbell any further information about this question? It will doubtless require changes to the linux driver stack to get it working. Yes, I have tried it, but eth1 still doesn’t work.